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International Journal of Innovation and Applied Studies
ISSN: 2028-9324     CODEN: IJIABO     OCLC Number: 828807274     ZDB-ID: 2703985-7
 
 
Thursday 12 December 2019

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Design and Performance Analysis of 1 bit Full Adder in Subthreshold Region using 45nm Technology


Volume 14, Issue 3, February 2016, Pages 817–823

 Design and Performance Analysis of 1 bit Full Adder in Subthreshold Region using 45nm Technology

Sajan Debnath1, Sayed Mohammad Reza Khurshid2, and Enamul Haque Talal3

1 Department of Electrical & Electronic Engineering, Metropolitan University, Sylhet, Bangladesh
2 Lecturer, Department of Electrical & Electronic Engineering, Metropolitan University, Sylhet, Bangladesh
3 Assistant Professor, Department of Electrical & Electronic Engineering, Metropolitan University, Sylhet, Bangladesh

Original language: English

Received 30 August 2015

Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract


Full adder is the fundamental block of any digital system like microprocessor, microcontroller, DSP (Digital Signal Processing). In this paper a new architecture of full adder optimized under sub

Author Keywords: Full adder, GDI, Delay, PDP, EDP.


How to Cite this Article


Sajan Debnath, Sayed Mohammad Reza Khurshid, and Enamul Haque Talal, “Design and Performance Analysis of 1 bit Full Adder in Subthreshold Region using 45nm Technology,” International Journal of Innovation and Applied Studies, vol. 14, no. 3, pp. 817–823, February 2016.