Volume 8, Issue 3, September 2014, Pages 1081–1089
Ishpal Kaur1, Gurinderpal Singh2, and Nancy Ramanpreet Kaur3
1 Department of E.C.E, CGC Groups of Colleges, Gharuan, Punjab, India
2 Department of E.C.E, CGC Groups of Colleges, Gharuan, Punjab, India
3 Department of E.C.E, CGC Groups of Colleges, Gharuan, Punjab, India
Original language: English
Copyright © 2014 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
SRAM cell design takes a big fraction of the entire power and die area in high performance processors. The overall power consumption in SRAM can be reduced either by decreasing the dynamic or static power. A Charge Recycling (CR) is a very efficient means to reduce the power dissipation in the write cycle of SRAM cell designs. To keep this point in view, this paper represents the simulation of four 64-bit SRAM cell topologies by using Charge Recycling scheme and their comparative analysis on the basis of their average write power consumption. The 64-bit SRAM cell designs are arranged in 8X8 form. Simulation reveals that 64-bit 9T SRAM cell with CR perform better than others in the term of power consumption but if die area and average power consumption both considers, then 64-bit 7T SRAM cell with CR perform well as compared to 64-bit 9T SRAM cell with CR. All the simulations of SRAM cell designs have been carried out on 180nm, 130nm and 100nm CMOS technology at 100 MHz and Vdd = 1.8 V.
Author Keywords: low power SRAM, power consumption, CR, charge recycling scheme, write cycle, 6T, 7T, 8T, 9T.
Ishpal Kaur1, Gurinderpal Singh2, and Nancy Ramanpreet Kaur3
1 Department of E.C.E, CGC Groups of Colleges, Gharuan, Punjab, India
2 Department of E.C.E, CGC Groups of Colleges, Gharuan, Punjab, India
3 Department of E.C.E, CGC Groups of Colleges, Gharuan, Punjab, India
Original language: English
Copyright © 2014 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
SRAM cell design takes a big fraction of the entire power and die area in high performance processors. The overall power consumption in SRAM can be reduced either by decreasing the dynamic or static power. A Charge Recycling (CR) is a very efficient means to reduce the power dissipation in the write cycle of SRAM cell designs. To keep this point in view, this paper represents the simulation of four 64-bit SRAM cell topologies by using Charge Recycling scheme and their comparative analysis on the basis of their average write power consumption. The 64-bit SRAM cell designs are arranged in 8X8 form. Simulation reveals that 64-bit 9T SRAM cell with CR perform better than others in the term of power consumption but if die area and average power consumption both considers, then 64-bit 7T SRAM cell with CR perform well as compared to 64-bit 9T SRAM cell with CR. All the simulations of SRAM cell designs have been carried out on 180nm, 130nm and 100nm CMOS technology at 100 MHz and Vdd = 1.8 V.
Author Keywords: low power SRAM, power consumption, CR, charge recycling scheme, write cycle, 6T, 7T, 8T, 9T.
How to Cite this Article
Ishpal Kaur, Gurinderpal Singh, and Nancy Ramanpreet Kaur, “Comparative Analysis of 64-bit Low Power SRAM Cell Designs by Using Charge Recycling Scheme,” International Journal of Innovation and Applied Studies, vol. 8, no. 3, pp. 1081–1089, September 2014.
