[ Conception et Co-Simulation sur Cible FPGA d’un Système d’Acquisition du Signal ECG par Modulation en Rapport Cyclique et Filtrage Dérivateur ]
Volume 31, Issue 4, January 2021, Pages 795–807
Steve Ulriche Otam1, E. R. Gamom Ngounou2, Jean Mbihi3, and Bertrand Moffo Lonla4
1 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
2 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
3 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
4 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
Original language: French
Copyright © 2021 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper presents a new acquisition and digital processing system of an ECG (Electrocardiogram) signal. The proposed technique is based on ECG signal processing in Matlab framework, using Duty Cycle Modulation (DCM) and IIR (infinite Impulse Response) derivative filter, with implementation into DsPBuilder. In fact, the detection of the R wave allows to extract the time interval between two consecutive R waves, in order to estimate the corresponding heart rate. Hence, the proposed simple algorithm consists of the following four relevant steps: derivative filtering, detection of peaks, elimination of bad peaks and calculation the heart rate. This algorithm considers that the acquisition of the ECG signal is done by duty cycle modulation, because in this case a simple low-pass decimation filter with bandwidth of 30Hz can simultaneously eliminates high frequency noise while extracting the ECG signal. The duty-cycle modulation circuit requires a maximum of 58 KHz frequency. Then, the digital part implemented using DsPBuilder blocks, consists of a decimation filter with 50 MHz sampling frequency, followed by the proposed algorithmic module. A virtual simulation and a Hardware-In-the-Loop (HIL) co-simulation using the DE10-NANO-SoC board with embedded FPGA-SoC 5CSEBA6U23I7, have been successfully conducted using imported signals into Matlab from Physionet.
Author Keywords: Duty Cycle Modulation, Electrocardiogram (ECG), Heart rate, FPGA target, hardware co-simulation.
Volume 31, Issue 4, January 2021, Pages 795–807
Steve Ulriche Otam1, E. R. Gamom Ngounou2, Jean Mbihi3, and Bertrand Moffo Lonla4
1 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
2 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
3 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
4 Research Laboratory of Computer Science Engineering and Automation City, ENSET, University of Douala, Douala, Cameroon
Original language: French
Copyright © 2021 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
This paper presents a new acquisition and digital processing system of an ECG (Electrocardiogram) signal. The proposed technique is based on ECG signal processing in Matlab framework, using Duty Cycle Modulation (DCM) and IIR (infinite Impulse Response) derivative filter, with implementation into DsPBuilder. In fact, the detection of the R wave allows to extract the time interval between two consecutive R waves, in order to estimate the corresponding heart rate. Hence, the proposed simple algorithm consists of the following four relevant steps: derivative filtering, detection of peaks, elimination of bad peaks and calculation the heart rate. This algorithm considers that the acquisition of the ECG signal is done by duty cycle modulation, because in this case a simple low-pass decimation filter with bandwidth of 30Hz can simultaneously eliminates high frequency noise while extracting the ECG signal. The duty-cycle modulation circuit requires a maximum of 58 KHz frequency. Then, the digital part implemented using DsPBuilder blocks, consists of a decimation filter with 50 MHz sampling frequency, followed by the proposed algorithmic module. A virtual simulation and a Hardware-In-the-Loop (HIL) co-simulation using the DE10-NANO-SoC board with embedded FPGA-SoC 5CSEBA6U23I7, have been successfully conducted using imported signals into Matlab from Physionet.
Author Keywords: Duty Cycle Modulation, Electrocardiogram (ECG), Heart rate, FPGA target, hardware co-simulation.
Abstract: (french)
Cet article présente un nouveau système d’acquisition et de traitement numérique du signal ECG (Electrocardiogramme). La technique proposée est basée sur le traitement du signal modulant ECG par Modulation en Rapport Cyclique (MRC) dans Matlab/Simulink implémentée avec DsPBuilder. En effet, la détection de l’onde R permet d’extraire l’intervalle de temps entre deux ondes R consécutives, en vue de déterminer la fréquence cardiaque correspondante. Ainsi l’algorithme simple proposé comporte quatre étapes importantes suivantes: le filtrage dérivatif, la détection des pics, l’élimination des mauvais pics et l’estimation de la fréquence cardiaque. Cet algorithme considère que l’acquisition du signal ECG se fait par modulation en rapport cyclique, car dans ce cas un simple filtre démodulateur passe-bas de bande passante 30Hz élimine en même temps les bruits hautes fréquences, et de d’extraire extraits le signal ECG. La modulation en rapport cyclique proposée admet une fréquence maximale 58 KHz. Puis, la partie numérique implémentée à l’aide des blocs DsPBuilder, est constituée d’un filtre décimateur de fréquence d’échantillonnage à 50MHz, suivi d’un module algorithmique proposé. Une simulation virtuelle et une Co-simulation HIL (Hardware-In-the-Loop) à base d’un FPGA DE10-NANO-SoC 5CSEBA6U23I7, ont été conduites avec succès en utilisant les données ECG issues de de la base de données Physionet.
Author Keywords: Modulation en Rapport Cyclique (MRC), Electrocardiogramme (ECG), rythme cardiaque, Cible FPGA, hardware Co-simulation.
How to Cite this Article
Steve Ulriche Otam, E. R. Gamom Ngounou, Jean Mbihi, and Bertrand Moffo Lonla, “Design and Co-Simulation on FPGA Target of an ECG Signal Acquisition System Using Duty-Cycle Modulation and Derivative Filtering,” International Journal of Innovation and Applied Studies, vol. 31, no. 4, pp. 795–807, January 2021.
