Volume 3, Issue 4, August 2013, Pages 1110–1115
S. Shurender1, K. Srividhya2, V. Mantharachalam3, K. Suresh4, and M. Umma Habiba5
1 Department of Electronics and Communication Engineering, Anna University, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India
2 Department of Electronics and Communication Engineering, Anna University, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India
3 RFTD, SAMEER, Tharamani, Chennai, India
4 RFTD, SAMEER, Tharamani, Chennai, India
5 Department of Electronics and Communication Engineering, Anna University, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India
Original language: English
Copyright © 2013 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
A phase locked loop based indirect frequency synthesizer is designed for S-band frequency. A Phase locked loop is designed and the phase noise response and transient response of the designed PLL is simulated for 2100MHz frequency. The phase noise response of total PLL and its individual components are obtained. A 3rd order low pass passive loop filter is used and by varying the loop bandwidth and phase margin the trade-off between lock time and phase noise is observed and an optimum value of loop bandwidth and phase margin is chosen such that its phase noise contribution is less. The designed phase locked loop has a low phase noise value of -112.4dBc/Hz at 100 kHz offset frequency and has a fast lock time of 119.5 us. The time taken by the designed frequency synthesizer to lock to 10 Hz frequency error and 1
Author Keywords: Phase locked loop, Integer-N PLL, Loop filter, Phase noise, Lock time.
S. Shurender1, K. Srividhya2, V. Mantharachalam3, K. Suresh4, and M. Umma Habiba5
1 Department of Electronics and Communication Engineering, Anna University, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India
2 Department of Electronics and Communication Engineering, Anna University, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India
3 RFTD, SAMEER, Tharamani, Chennai, India
4 RFTD, SAMEER, Tharamani, Chennai, India
5 Department of Electronics and Communication Engineering, Anna University, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India
Original language: English
Copyright © 2013 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
A phase locked loop based indirect frequency synthesizer is designed for S-band frequency. A Phase locked loop is designed and the phase noise response and transient response of the designed PLL is simulated for 2100MHz frequency. The phase noise response of total PLL and its individual components are obtained. A 3rd order low pass passive loop filter is used and by varying the loop bandwidth and phase margin the trade-off between lock time and phase noise is observed and an optimum value of loop bandwidth and phase margin is chosen such that its phase noise contribution is less. The designed phase locked loop has a low phase noise value of -112.4dBc/Hz at 100 kHz offset frequency and has a fast lock time of 119.5 us. The time taken by the designed frequency synthesizer to lock to 10 Hz frequency error and 1
Author Keywords: Phase locked loop, Integer-N PLL, Loop filter, Phase noise, Lock time.
How to Cite this Article
S. Shurender, K. Srividhya, V. Mantharachalam, K. Suresh, and M. Umma Habiba, “Design of S-Band Frequency Synthesizer for Microwave Applications,” International Journal of Innovation and Applied Studies, vol. 3, no. 4, pp. 1110–1115, August 2013.
