SRAM cell design takes a big fraction of the entire power and die area in high performance processors. The overall power consumption in SRAM can be reduced either by decreasing the dynamic or static power. A Charge Recycling (CR) is a very efficient means to reduce the power dissipation in the write cycle of SRAM cell designs. To keep this point in view, this paper represents the simulation of four 64-bit SRAM cell topologies by using Charge Recycling scheme and their comparative analysis on the basis of their average write power consumption. The 64-bit SRAM cell designs are arranged in 8X8 form. Simulation reveals that 64-bit 9T SRAM cell with CR perform better than others in the term of power consumption but if die area and average power consumption both considers, then 64-bit 7T SRAM cell with CR perform well as compared to 64-bit 9T SRAM cell with CR. All the simulations of SRAM cell designs have been carried out on 180nm, 130nm and 100nm CMOS technology at 100 MHz and Vdd = 1.8 V.