This work focuses on the structure of the duty cycle modulator analog-to-digital converter. We propose to model again its complete chain, this time by parallelizing its demodulator filter. More specifically, we want to optimize the performance of this type of converter that no longer needs to make this proof in the field of real-time digital conversion. Thus, we will thanks to the so-called residue method, make parallel the classic demodulation filter and thereby obtain a new conversion chain. Following up with software tools such as MATLAB; System Generator and ISE Xilinx, we implement and simulate this new analog/digital converter chain with duty cycle modulator. After this implementation and simulation which uses as input signal, a sinusoid at a frequency of f = 30Hz, the results obtained show us that it is more judicious and advantageous to use this new conversion chain because with a quadratic error E = 0.8208, we do not lose the quality of the signal but we save in hardware resources; with a harmonic distortion rate THD = 0.6099, we have a type of converter that further reduces harmonics, and offers us a demodulation time saving of about 76,2%.